TI Obsoletes FPGA

TI Obsoletes FPGA

Mixes ARM cores with DSPs and programmable logic

R. Colin Johnson

PORTLAND, Ore. — Texas Instruments (TI) — king of the DSP — is at it again, this time targeting the FPGA market with a 9 processor jack-of-all-trades device capable of radically downsizing mammoth avionic, military, test and measurement and medical instruments — from backpack radars to portable magnetic resonance instruments (MRIs).

According to TI, the Keystone-II (66AK2L06) solution allows devices using it to be 66 percent smaller, consume 60 percent less power, cost 50 percent less and are 3-times faster to market than using an FPGA solution.

"Our newest Keystone II system-on-chip [SoC] has two ARM's Cortex A15 MPCore processors, four 1.2 GHz C66x DSPs [digital signal processors) and four programmable accelerators," Robert Ferguson, communications processors business development manager at TI told EE Times.

TI's FPGA-killer is an SoC with two ARM cores, four DSPs and four programmable hardware accelerators all connected by TeraNet on-chip and by four lanes of 7.8-Gbit JESD204B interfaces off-chip.
(Source: TI)

That spells significant system-level savings for high-speed data acquisition when paired with 4-lanes of JEDEC-compatible input/output (I/O) running at 7.3 Gbits/sec per lane (JESD204B).

The four on-chip accelerators are connected to the other six cores, and each other, with TI's on-chip TeraNet. The four accelerators include a programmable digital-radio front-end (DFE), two programmable Fast Fourier Transform coprocessors (FFTCs), a programmable security accelerator for high-speed encryption/decryption and a packet accelerator for network coprocessor (NETCP) for operations like header matching, and packet modification operations, connected to four gigabit Ethernet (GbE) modules to send and receive packets.

Typical configuration for test & measurement, avionics and defense applications
(Source: TI)

"The DFE gives us the capability for 48 high-speed digital down converter/up converter channels [DDUC] that also handle digital filtering," Ferguson told us.

TI is also supporting its newest Keystone II offering with its complete suite of software development tools as well as a full reference design — which can be downloaded for customizing or purchased on a multi-tier board ready-to-run.

The Keystone-II 66AK2L06 consumes just 12 watts — a fraction of what an FPGA-based solution consumes — "enabling up to a 50 percent cost and power reduction compared to FPGAs," Sameer Wasson, general manager of Communications Processors at TI, told us. "We believe customers will be able to develop their devices three times faster than when using FPGAs — in days rather than weeks."

TI's newest Keystone-II SoC also is pre-validated for use with TI's family of analog front ends (AFEs), analog-to-digital converters (A/Ds) and digital-to-analog converters (D/As) including the 12-bit, 4-GigaSample (GSPS) the ADC12J4000, the 16-bit, 250-MegaSample (MSPS) ADS42JB69 as well as TI's high-speed DACs, such as the 16-bit, 2.5-GSPS DAC38J84 as well as TI's clocks, including the LMK04828 clock jitter cleaner. It also can make use of TI's Multicore software Development Kit (MCSDK) and its radio-frequency (RF) Software Development Kit (RFSDK).

— R. Colin Johnson, Advanced Technology Editor, EE Time